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may 2004 1/56 this is preliminary information on a new product now in development. details are subject to change without notice. version 1.1 STV6889 high-end i2c controlled deflection processor for multisync monitor product preview features general ? advanced i 2 c-bus controlled deflection processor dedicated for high-end crt monitors ? single supply voltage 12v ? very low jitter ? dc/dc converter controller ? advanced ew drive ? advanced asymmetry corrections ? automatic multistandard synchronization ? vertical dynamic correction waveform output ? x-ray protection and soft-start & stop on horizontal and dc/dc drive outputs ?i 2 c-bus status register horizontal section ? 150 khz maximum frequency ? corrections of geometric asymmetry: pin cushion asymmetry, parallelogram, separate top/bottom corner asymmetry ? tracking of asymmetry corrections with vertical size and position ? fully integrated horizontal moir cancellation vertical section ? 200 hz maximum frequency ? vertical ramp for dc-coupled output stage with adjustments of: c-correction, s-correction for super-flat crt, vertical size, vertical position ? vertical size and position prescales for factory adjustment ? vertical moir cancellation through vertical ramp waveform ? compensation of vertical breathing with eht variation; i 2 c-bus gain adjustment ew section ? symmetrical geometry corrections: pin cushion, keystone, top/bottom corners separately, s- and w-corrections ? horizontal size adjustment ? tracking of ew waveform with vertical size and position, horizontal size and frequency ? compensation of horizontal breathing with eht variation, i 2 c-bus gain adjustment dynamic correction section ? generates vertical waveform for dynamic corrections like focus, brightness uniformity, ... ? 1 output with vertical dynamic correction waveform, both polarities, tracking with vertical size and position dc/dc controller section ? step-up and step-down conversion modes ? external sawtooth configuration ?i 2 c-bus-controlled output voltage ? synchronized on hor. frequency with phase selection ? selectable polarity of drive signal ? protection at h unlock condition description the STV6889 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. this ic controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. combined with other st components dedicated for crt monitors (microcontroller, video preampli- fier, video amplifier, osd controller), the STV6889 allows fully i 2 c bus-controlled computer display monitors to be built with a reduced number of ex- ternal components. sdip 32 (shrink dip package) order code: STV6889 1
table of contents 3 2/56 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin function reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 electrical parameters and operating conditions . . . . . . . . . . . . . . . . . . . . . . 9 6.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 supply and reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.6 ew drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8 dc/dc controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 typical output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 i2c-bus control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 supply and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.1 power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.2 i2c-bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 synchronization processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.1 synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.2 sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.3 mcu controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.4 automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.2 pll1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3.3 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3.4 pll2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1
STV6889 3/56 9.3.5 dynamic pll2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3.6 output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 9.3.7 soft-start and soft-stop on h-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3.8 horizontal moir cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.4 vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.2 s and c corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.3 vertical breathing compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.4 vertical after-gain and offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.5 vertical moir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.6 biasing of vertical booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 ew drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.6.1 vertical dynamic correction output vdycor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7 dc/dc controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7.1 synchronization of dc/dc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7.2 soft-start and soft-stop on b-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.8 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8.1 safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 9.8.2 composite output hlckvbk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 internal schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1
STV6889 4/56 1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 h/hvsyn vsyn hlckvbk hpll2c co hgnd ro hpll1f hposf ic hfly refout bcomp bregin bisense hoscf hehtin vehtin voscf vagccap vgnd vcap vout ewout xray hout gnd bout vcc scl sda vdycor 2
STV6889 5/56 2 block diagram horizontal vco phase/frequency comparator horizontal position lock detection pll1 v-sync detection input selection polarity handling vertical oscillator with agc pll2 phase comparator phase shifter h duty controller pin cushion asymm. parallelogram top corner asymm. bottom corner asymm. hor. duty cycle h-drive buffer h-moir controller h-moir amplitude v-sync extraction & detection tracking v-dynamic correction (focus, brightness) vdycor amplitude h-sync detection polarity handling v-blank h-lock safety processor i2c-bus interface supply supervision reference generation b+ dc/dc converter controller b+ ref. v-ramp control vertical size & pos. prescale size & pos. vertical moir ew generator pin cushion keystone top corners bottom corners internal ref. : multiple bit djustments h size s-correction w-correction s- & c-correction pll1 speed h/hvsyn hlckvbk sda scl vcc refout gnd vsyn vgnd voscf vagccap vcap vdycor vout vehtin hehtin ewout ic bcomp bregin bisense bout xray hout hpll2c hfly hoscf co ro hpll1f hposf hgnd breathing gain breathing gain 10 23 18 17 24 11 14 15 16 28 25 26 5 12 4 6 8 9 7 1 3 31 30 29 13 27 2 21 19 20 22 32 STV6889 i2c-bus control registers
STV6889 6/56 3 pin function reference pin name function 1 h/hvsyn ttl compatible h orizontal / h orizontal and v ertical syn c. input 2 vsyn ttl compatible v ertical syn c. input 3 hlckvbk h orizontal pll1 l o ck detection and v ertical early b lan k ing composite output 4 hoscf high h orizontal osc illator sawtooth threshold level f ilter input 5 hpll2c h orizontal pll2 loop c apacitive filter input 6 co horizontal o scillator c apacitor input 7 hgnd h orizontal section g rou nd 8 ro horizontal o scillator r esistor input 9 hpll1f h orizontal pll1 loop f ilter input 10 hposf h orizontal pos ition f ilter and soft-start time constant capacitor input 11 ic i nternally c onnected (to be left open) 12 hfly h orizontal fly back input 13 refout ref erence voltage out put 14 bcomp b + dc/dc error amplifier ( comp ensation) output 15 bregin reg ulation feedback in put of the b + dc/dc converter controller 16 bisense b + dc/dc converter current ( i ) sense input 17 hehtin in put for compensation of h orizontal amplitude versus eht variation 18 vehtin in put for compensation of v ertical amplitude versus eht variation 19 voscf v ertical osc illator sawtooth low threshold f ilter (capacitor to be connected to vgnd) 20 vagccap input for storage cap acitor for a utomatic g ain c ontrol loop in v ertical oscillator 21 vgnd v ertical section g rou nd 22 vcap v ertical sawtooth generator cap acitor 23 vout v ertical deflection drive out put for a dc-coupled output stage 24 ewout e / w out put 25 xray x - ray protection input 26 hout h orizontal drive out put 27 gnd main g rou nd 28 bout b + dc/dc converter controller out put 29 vcc supply voltage 30 scl i2c-bus s erial cl ock input 31 sda i2c-bus s erial da ta input/output 32 vdycor v ertical dy namic cor rection output
STV6889 7/56 4 quick reference data characteristic value unit general package sdip 32 supply voltage 12 v supply current 65 ma application category high-end means of control ? maximum clock frequency i2c-bus ? 400 khz ew drive yes dc/dc converter controller yes horizontal section frequency range 15 to 150 khz autosync frequency ratio (can be enlarged in application) 4.28 positive ? negative polarity of horizontal syn c signal ? automatic adaptation yes ? yes ? yes duty cycle range of the drive signal 30 to 65 % position adjustment range with respect to h period 10 % soft start ? soft stop feature yes ? yes hardware ? software pll lock indication yes ? yes parallelogram yes pin cushion asymmetry correction (also called side pin balance) yes top ? bottom ? common corner asymmetry correction yes ? yes ? no tracking of asymmetry corrections wi th vertical size & position yes horizontal moir cancellation (int.) for combined ? separated architecture yes ? yes vertical section frequency range 35 to 200 hz autosync frequency range (150nf at vcap and 470nf at vagccap) 50 to 180 hz positive ? negative polarity of vertical syn c signal ? automatic adaptation yes ? yes ? yes s-correction ? c-correction ? super-flat tube characteristic yes ? yes ? yes vertical size ? vertical position ? prescale adjustments yes ? yes ? yes vertical moir cancellation (internal) yes eht breathing compensation ? with i2c-bus gain control yes ? yes ew section pin cushion correction yes keystone correction yes top ? bottom ? common corner correction yes ? yes ? no s-correction ? w-correction yes ? yes horizontal size adjustment yes tracking of ew waveform with frequency ? vertical size & position yes ? yes eht breathing compensation ? with i2c-bus gain control yes ? yes dynamic correction section (dyn. focus, dyn. brightness,...) vertical dynamic correction output vdycor ? positive or negative polarity yes ? yes horizontal dynamic correction output hdycor no composite hv dynamic correction output hvdycor ? positive or negative polarity no ? no shape control on h waveform component of hvdycor output no tracking of horizontal waveform component with horizontal size ? eht no ? no tracking of vertical waveforms (component) with v. size & position yes dc ? dc controller section step-up ? step-down conversion mode yes ? yes internal ? external sawtooth configuration no ? yes bus-controlled output voltage ? inhibition at h unlock yes ? yes mute ? soft start ? soft stop feature yes ? yes ? yes positive (n-mos) ? negative(p-mos) polarity of bout signal yes ? yes phase selection ? max current selection ? frequency selection yes ? yes ? yes
STV6889 8/56 5 absolute maximum ratings all voltages are given with respect to ground. currents flowing from the device (sourced) are signed negative. currents flowing to the device are signed positive. symbol parameter value unit min max v cc supply voltage (pin vcc ) -0.4 13.5 v v (pin) pins hehtin , vehtin , xray , hout , bout pins h/hvsyn , vsyn , scl , sda pins hlckvbk , co , ro , hpll1f , hposf , bregin , bisense , vagccap , vcap , vdycor , hoscf , voscf pin hpll2c pin hfly -0.4 -0.4 -0.4 -0.4 -0.4 v cc 5.5 v refo v refo /2 v refo v v v v v i latch(pin) latch-up current all pins except xray pin xray -200 -100 200 200 ma ma v esd esd susceptibility (human body model: discharge of 100pf through 1.5k ) -2000 2000 v t stg storage temperature -40 150 c t j junction temperature 150 c
STV6889 9/56 6 electrical parameters and operating conditions medium (middle) value of an i2c-bus control or adjustm ent register composed of bits d0, d1,...,dn is the one having dn at "1" and all other bits at "0". minimum value is the one with all bits at 0, maximum value is the one with all at "1". currents flowing from the device (sourced) are signed negative. currents flowing to the device are signed positive. t h is period of horizontal deflection. 6.1 thermal data 6.2 supply and reference voltages t amb = 25c 6.3 synchronization inputs vcc = 12v, t amb = 25c symbol parameter value unit min. typ. max. t amb operating ambient temperature 0 70 c r th(j-a) junction-ambience thermal resistance 65 c/w symbol parameter test conditions value units min. typ. max. v cc supply voltage at vcc pin 10.8 12 13.2 v i cc supply current to vcc pin v cc = 12v 65 ma v refo reference output voltage at refout pin v cc = 12v, i refo = -2ma 7.65 7.9 8.2 v i refo current capability of refout output -5 0 ma symbol parameter test conditions value units min. typ. max. v loh/hvsyn low level voltage on h/hvsyn 00.8v v hih/hvsyn high level voltage on h/hvsyn 2.2 5 v v lovsyn low level voltage on vsyn 00.8v v hivsyn high level voltage on vsyn 2.2 5 v r pdsyn internal pull-down on h/hvsyn , vsyn 100 175 250 k t pulsehsyn h sync. pulse duration on h/hvsyn pin 0.5 s t pulsehsyn proportion of h sync pulse to h period pin h/hvsyn 0.2 t pulsevsyn v sync. pulse duration pins h/hvsyn , vsyn 0.5 750 s t pulsevsyn proportion of v sync pulse to v period pins h/hvsyn , vsyn 0.15 t extrv proportion of h sync pulse length to h pe- riod for extraction as v sync pulse pin h/hvsyn , cap. on pin co = 820pf 0.21 0.35 t hpoldet polarity detection time (after change) pin h/hvsyn 0.75 ms /t h /t v /t h
STV6889 10/56 6.4 horizontal section table 1. horizontal section ( vcc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. pll1 i ro current load on ro pin 1.5 ma c co capacitance on co pin 390 pf f ho frequency of hor. oscillator 150 khz f ho(0) free-running frequency of hor. oscill. ( 1 ) r ro =5.23k , c co =820pf 27 28.5 29.9 khz f hocapt hor. pll1 capture frequency ( 4 ) f ho(0) = 28.5khz 29 122 khz temperature drift of free-running freq. ( 3 ) -150 ppm/c f ho v ho average horizontal oscillator sensitivity f ho(0) = 28.5khz 20.2 khz/v v ho h. oscill. control voltage on pin hpll1f v refo =8v 1.4 6.0 v v hothrfr threshold on h. oscill. control voltage on hpll1f pin for tracking of ew with freq. v refo =8v 5.0 v v hposf control voltage on hposf pin hpos (sad01h): 11111111b 10000000b 00000000b 2.8 3.4 4.0 v v v v hothrlo bottom of hor. oscillator sawtooth ( 6 ) 1.6 v v hothrhi top of hor. oscillator sawtooth ( 6 ) 6.4 v pll2 r in(hfly) input impedance on hfly input v (hfly) > v thrhfly ( 2 ) 300 500 700 i inhfly current into hfly input at top of h flyback pulse 5 ma v thrhfly voltage threshold on hfly input 0.5 0.6 v v s(0) h flyback lock middle point ( 6 ) no pll2 phase modula- tion 4.0 v v bothpll2c low clamping voltage on hpll2c pin ( 5 ) 1.6 v v tophpll2c high clamping voltage on hpll2c pin ( 5 ) 4.0 v t ph (min) min. advance of h-drive off before middle of h flyback ( 7 ) null asym. correction 0 % t ph (max) max. advance of h-drive off before middle of h flyback ( 8 ) null asym. correction 44 % h-drive output on pin hout i hout current into hout output output driven low 30 ma t hoff duty cycle of h-drive signal f h = 31khz; hduty (sad00h): x1111111b x0000000b soft-start/soft-stop value 27 65 85 % % % f ho 0 f ho 0 t -------------------------- /t h /t h /t h
STV6889 11/56 notes about horizontal section note 1: frequency at no sync signal condition. for correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. the application must consider the spread of values of real electrical components in r ro and c co positions so as to always meet this condition. the formula to calculate the free-running frequency is f ho(0) =0.122/(r ro c co ) note 2: base of npn transistor with emitter to ground is internally connected on pin hfly through a series resistance of about 500 and a resistance to ground of about 20k note 3: evaluated and figured out during the device qualification phase. informative. not tested on every single unit. note 4: this capture range can be enlarged by external circuitry. note 5: the voltage on hpll2c pin corresponds to immediate phase of leading edge of h-drive signal on hout pin with respect to internal horizontal oscillator sawtooth. it must be between the two clamping levels given. voltage equal to one of the clamping values indicates a marginal operation of pll2 or non-locked state. note 6: internal threshold. see figure 6 . note 7: the t ph (min) parameter is fixed by the application. for correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. marginal situation is indicated by reach of v tophpll2c high clamping level by waveform on pin hpll2c . also refer to note 5 and figure 6 . picture geometry corrections through pll1 & pll2 t hph hor. vco phase vs. sync signal (via pll1), see figure 7 hpos (sad01h): 11111111b 10000000b 00000000b +11 0 -11 % % % t pcac contribution of pin cushion asymmetry correction to phase of h-drive vs. static phase (via pll2), measured in corners pcac (sad11h) full span ( 9 ) vpos at medium vsize at minimum vsize at medium vsize at maximum 0.9 1.6 2.6 % % % t paralc contribution of parallelogram correction to phase of h-drive vs. static phase (via pll2), measured in corners paral (sad12h) full span ( 9 ) vpos at medium vsize at minimum vsize at medium vsize at maximum 1.4 1.9 2.4 % % % t tcac contribution of top corner asymmetry correction to phase of h-drive vs. static phase (via pll2), measured in corners tcac (sad13h) full span ( 9 ) vpos at medium vsize at minimum vsize at medium vsize at maximum 0.4 1.4 3.5 % % % t bcac contribution of bottom corner asymmetry correction to phase of h-drive vs. static phase (via pll2), measured in corners bcac (sad14h) full span ( 9 ) vpos at medium vsize at minimum vsize at medium vsize at maximum 0.4 1.4 3.5 % % % table 1. horizontal section ( vcc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. /t h /t h /t h /t h /t h
STV6889 12/56 notes about horizontal section (continued) note 8: the t ph (max) parameter is fixed by the application. for correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. marginal situation is indicated by reach of v bothpll2c low clamping level by waveform on pin hpll2c . also refer to note 5 and figure 6 . note 9: all other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions. 6.5 vertical section table 2. vertical section (vcc = 12v, tamb = 25c) symbol parameter test conditions value units min. typ. max. agc-controlled vertical oscillator sawtooth; v refo = 8v r l(vagccap) ext. load resistance on vagccap pin ( 10 ) v amp /v amp (r= ) 1% 65 m v vob sawtooth bottom voltage on vcap pin ( 11 ) no load on voscf pin ( 11 ) 2v v votref sawtooth top voltage internal ref- erence 5v v vot sawtooth top voltage on vcap pin agc loop stabilized 5 v t vodis sawtooth discharge time c vcap =150nf 80 s f vo(0) free-running frequency c vcap =150nf 100 hz f vocapt agc loop capture frequency c vcap =150nf 50 185 hz sawtooth non-linearity ( 12 )( 17 ) agc loop stabilized ( 12 ) 0.5 % frequency drift of sawtooth amplitude ( 18 )( 19 ) agc loop stabilized f vocapt (min) f vo f vocapt (max) 200 ppm/hz vertical output drive signal (on pin vout ); v refo = 8v v midref internal reference for vertical sawtooth middle point 3.5 v v mid(vout) middle point on vout sawtooth vpos (sad08h): ( 22 ) x0000000b x1000000b x1111111b vpof (sad1eh): ( 21 ) x0000000b x1000000b x1111111b 3.65 3.1 3.45 3.8 3.3 3.45 3.6 3.3 v v v v v v v amp amplitude of vout sawtooth (peak-to-peak voltage) vsize (sad07h): ( 23 ) x0000000b x1000000b x1111111b vsag (sad1dh): ( 20 ) x0000000b x1000000b x1111111b 3.5 2.25 3.0 3.75 2 2.5 3.0 2.5 v v v v v v v offvout level on vout pin at v-drive "off" i2c-bus bit vouten at 0 4.0 v v vodev v voamp -------------------- v voamp v voamp f vo ----------------------------------
STV6889 13/56 notes about vertical section note 10: value of acceptable cumulated parasitic load resistance due to humidity, agc storage capacitor leakage, etc., for less than 1% of v amp change. note 11: the threshold for v vob is generated internally and routed to voscf pin. any dc current on this pin will influence the value of v vob . note 12: maximum of deviation from an ideally linear sawtooth ramp at null s-correction ( scor at 0000000b) and null c-correction ( ccor at 1000000b). the same rate applies to v-drive signal on vout pin, no effect on ewout . note 13: maximum s-correction ( scor at x1111111b), null c-correction ( ccor at 1000000b). note 14: null s-correction ( scor at 0000000b). note 15: "t vr " is time from the beginning of vertical ramp of v-drive signal on vout pin. "t vr " is the duration of this ramp, see chapter 7 - page 21 and figure 17 . note 16: if v veht = v vehtnull or v heht = v hehtnull , respectively, the influence of v veht on vertical drive amplitude or the influence of v heht on ew drive signal, respectively, is null. note 17: v voamp = v vot - v vob note 18: only the top of the saw tooth drifts. the same rate applies to v-drive signal on vout pin. note 19: informative, not tested on each unit. note 20: vsize at medium value 1000000b. note 21: vpos at medium value 1000000b. note 22: vpof at medium value 1000000b. note 23: vsag at maximum value 1111111b. i vout current delivered by vout output -5 0.25 ma v scor s-correction range ( 13 )( 20 )( 21 ) agc loop stabilized t vr =1/4 t vr ( 15 ) t vr =3/4 t vr -4.5 +4.5 % % v ccor c-correction range ( 14 )( 20 )( 21 ) agc loop stabilized t vr =1/2 t vr ( 15 ) ccor (sad0ah): x0000000b x1000000b x1111111b -2.5 0 +2.5 % % % v veht control input voltage range on- vehtin pin 146v v vehtnull neutral point on breathing char- acteristics ( 16 ) 4.0 v breathing compensation v refo v veht v cc v veht (min) v veht v ve- ht (max) : vehtg (sad1ch): x0000000b x1000000b x1111111b 0 5 0 -5 %/v %/v %/v %/v table 2. vertical section (vcc = 12v, tamb = 25c) symbol parameter test conditions value units min. typ. max. /v am p /v am p v amp v amp v veht -----------------------------------
STV6889 14/56 6.6 ew drive section table 3. ew drive section (v cc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. v ew output voltage on ewout pin 1.8 6.5 v i ewout current delivered by ewout out- put -1.5 0.1 ma v heht control voltage range on heh- tin pin 16v v hehtnull neutral point on breathing char- acteristics. see figure 15 . ( 16 ) 4.0 v v ew-dc dc component of the ew-drive signal on ewout pin ( 30 ) ( 24 )( 25 )( 26 )( 27 )( 28 )( 36 )( 42 )( 43 ) ewtrhfr 0 or v ho v hothrfr hsize (sad10h): 00000000b 10000000b 11111111b 2 3.25 4.5 v v v v ew-base dc reference for the ew-drive signal on ewout pin 2v breathing compensation on dc component of the ew-drive sig- nal ( 30 ) ( 24 )( 25 )( 26 )( 27 )( 42 )( 43 ) v refo v heht v cc v heht (min) v heht v he- ht (max) : hehtg (sad1bh): x0000000b x1000000b x1111111b 0 0 -0.25 0 +0.25 v/v v/v v/v v/v v/v temperature drift of dc compo- nent of the ew-drive signal ( 30 ) ( 24 )( 25 )( 26 )( 27 )( 28 )( 36 )( 42 )( 43 ) ( 44 ) 100 ppm/c v ew-pcc pin cushion correction compo- nent of the ew-drive signal ( 24 )( 25 )( 26 )( 28 )( 29 )( 31 ) ( 32 )( 36 )( 42 )( 43 ) vsize at maximum pcc (sad0ch): x0000000b x1000000b x1111111b tracking with vsize : pcc at x1000000b vsize (sad07h): x0000000b x1000000b 0 0.75 1.5 0.25 0.5 v v v v v tracking of pcc component of the ew-drive signal with vertical position adjustment ( 24 )( 25 )( 26 )( 29 )( 33 )( 35 )( 36 )( 42 )( 43 ) pcc at x1111111b vpos (sad08h): x0000000b x1111111b 0.5 2.0 v ew-key keystone correction component of the ew-drive signal ( 25 )( 26 )( 27 )( 28 )( 29 )( 33 )( 34 )( 36 )( 42 )( 43 ) keyst (sad0dh): x0000000b x1111111b 0.4 -0.4 v v v ew dc ? v heht ----------------------- v ew dc ? v ew dc ? t ------------------------------- - v ew pcc ? t vr 0 =
v ew pcc ? t vr t vr =
--------------------------------------------
STV6889 15/56 v ew-tcor top corner correction compo- nent of the ew-drive signal ( 24 )( 26 )( 27 )( 28 )( 29 )( 31 )( 33 )( 36 )( 42 ) ( 43 ) tcc (sad0eh): x0000000b x1000000b x1111111b -1.4 0 +1.4 v v v v ew-bcor bottom corner correction compo- nent of the ew-drive signal ( 24 )( 25 )( 27 )( 28 )( 29 )( 32 )( 33 )( 36 )( 42 ) ( 43 ) bcc (sad0fh): x0000000b x1000000b x1111111b -1.4 0 +1.4 v v v v ew-s pin cushion s correction compo- nent of ew-drive signal ( 24 )( 25 )( 26 )( 27 )( 28 )( 29 )( 33 )( 36 )( 41 ) ( 43 ) ewsc (sad19h): x0000000b x1000000b x1111111b -0.3 0 0.3 v v v v ew-w pin cushion w correction com- ponent of ew-drive signal ( 24 )( 25 )( 26 )( 27 )( 28 )( 29 )( 33 )( 36 )( 41 ) ( 42 ) ewwc (sad1ah): x0000000b x1000000b x1111111b -0.1 0 0.1 v v v tracking of ac component of ew-drive signal with horizontal frequency ( 37 )( 38 )( 39 ) i2c bit ewtrhfr =1 v ho v hothrfr v ho (min) v ho v hothrfr 0 20 %/v %/v tracking of dc component of ew-drive signal with horizontal frequency ( 30 )( 38 )( 39 ) i2c bit ewtrhfr =1 v ho v hothrfr v ho (min) v ho v hothrfr 0 20 %/v %/v tracking of ac component of ew-drive signal with horizontal size ( 37 ) i2c bit ewtrhsize =1 hsize (sad10h): 00000000b 10000000b 11111111b 138 119 100 % % % breathing compensation on ac component of the ew-drive sig- nal ( 37 ) v refo v heht v cc v heht (min) v heht v he- ht (max) : hehtg (sad1bh): 0000000b 1000000b 1111111b 0 3.5 0 -3.5 %/v %/v %/v %/v table 3. ew drive section (v cc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. v ew ac ? v ew ac ? f max
v ho ----------------------------------------------------- - v ew dc ? v ew dc ? span
v ho ---------------------------------------------------- - v ew ac ? v ew ac ? hsize max
-------------------------------------------------- - v ew ac ? v ew ac ? v heht ------------------------------------------ -
STV6889 16/56 notes about ew drive section note 24: keyst at medium (neutral) value. note 25: tcc at medium (neutral) value. note 26: bcc at medium (neutral) value. note 27: pcc at minimum value. note 28: vpos at medium (neutral) value. note 29: hsize i2c field at maximum value. note 30: v ew-dc is defined as voltage at t vr =1/2 t vr . note 31: defined as difference of (voltage at t vr =0) minus (voltage at t vr =1/2 t vr ). note 32: defined as difference of (voltage at t vr =t vr ) minus (voltage at t vr =1/2 t vr ). note 33: vsize at maximum value. note 34: difference (voltage at t vr =0) minus (voltage at t vr =t vr ). note 35: ratio "a/b"of parabola component voltage at t vr =0 versus parabola component voltage at t vr =t vr . see figure 2 . note 36: v heht v refo , v veht v refo note 37: v ew-ac is defined as overall peak-to-peak value between t vr =0 and t vr =t vr of all components other than v ew- dc (contribution of pcc, keystone correction, corner corrections and s- and w-corrections). note 38: more precisely tracking with voltage on hpll1f pin which itself depends on frequency at a rate given by external components on pll1 pins note 39: v ew-dc [span] = v ew-dc [ v ho v hothrfr ] - v ew-dc [ hsize =0000000b]. v ew-ac [f max ] = v ew-ac [ v ho v hothrfr ]. note 40: defined as difference of (voltage at t vr =1/4 t vr ) minus (voltage at t vr =3/4 t vr ). note 41: defined as difference of (voltage at t vr =1/2 t vr ) minus (voltage at t vr =1/4 t vr ). note 42: ewsc at medium (neutral) value. note 43: ewwc at medium (neutral) value. note 44: informative, not tested on each unit.
STV6889 17/56 6.7 dynamic correction outputs section notes about dynamic output section note 45: ratio "a/b"of vertical parabola component voltage at t vr =0 versus vertical parabola component voltage at t vr =t vr . table 4. dynamic correction outputs section ( v cc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. vertical dynamic correction output vdycor i vdycor current delivered by vdycor output -1.5 0.1 ma v vd-dc dc component of the drive signal on vdycor output r l(vdycor) =10k 4v v vd-v amplitude of v-parabola on vdycor output ( 28 ) vsize at medium vdc-amp (sad15h): x0000000b x1000000b x1111111b vdc-amp at maximum vsize (sad07h): x0000000b x1111111b 0 0.5 1 0.6 1.6 v v v v v tracking of v-parabola on vdycor output with vertical position ( 45 ) vdc-amp at maximum vpos (sad08h): x0000000b x1111111b 0.5 2.0 v vd v ? t vr 0 =
v vd v ? t vr t vr =
-------------------------------------------------------
STV6889 18/56 6.8 dc/dc controller section note 46: a current sink is provided by the bcomp output while bout is disabled. note 47: internal reference related to v refo . the same values to be found on pin bregin , while regulation loop is stabilized. note 48: only applies to configuration specified in "test conditions" column, i.e. synchronization of bout ?off-to-on? edge with horizontal fly-back signal. refer to chapter "dc/dc controller" for more details. table 5. dc/dc controller section (v cc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. r b+fb ext. resistance applied between bcomp output and bregin input 5k a olg open loop gain of error amplifier on bregin input low frequency ( 19 ) 100 db f ugbw unity gain bandwidth of error amplifier on bregin input ( 19 ) 6mhz i ri bias current delivered by bregin -0.2 a i bcomp output current capability of bcomp out- put. bout enabled bout disabled ( 46 ) -0.5 0.5 2.0 ma ma a bisense voltage gain on bisense input 3 v thrbiscurr threshold voltage on bisense input corresponding to current limitation thrblsense = 0 thrblsense = 1 tbd tbd 2.1 1.2 v i bisense bias current delivered by bisense -1 a t bon conduction time of the power transistor t h - 300ns i bout output current capability of bout output 0 10 ma v bosat saturation voltage of the internal output transistor on bout i bout =10ma 0.25 v v breg regulation reference for bregin volt- age ( 47 ) v refo =8v bref (sad03h): x0000000b x1000000b x1111111b 3.8 4.9 6.0 v v v t btrigdel delay of bout ?off-to-on? edge after middle of flyback pulse ( 48 ) boutph = 0 and bo- hedge = 0 16 % /t h
STV6889 19/56 6.9 miscellaneous table 6. miscellaneous ( v cc = 12v, t amb = 25c) symbol parameter test conditions value units min. typ. max. vertical blanking and horizontal lock indication composite output hlckvbk i sinklckbk sink current to hlckvbk pin ( 49 ) 100 a v olckbk output voltage on hlckvbk output 0.1 1.1 5 6 v v v v horizontal moir canceller modulation of t h by h. moir function hmoirmode = 0 hmoire (sad02h): x0000000b x1111111b hmoirmode = 1 hmoire (sad02h): x0000000b x1111111b 0 0.02 0 0.04 % % % % vertical moir canceller v v-moir amplitude of modulation of v-drive sig- nal on vout pin by vertical moir. vmoire (sad0bh): x0000000b x1111111b 0 3 mv mv protection functions v thrxray input threshold on xray input ( 50 ) v refo -10mv v refo v refo +10mv t xraydelay delay time between xray detection event and protection action t h 2t h v ccxrayen minimum v cc value for operation of xray detection and protection ( 53 ) 10.2 10.8 v v ccen v cc value for start of operation at v cc ramp-up ( 51 ) 8.0 v v ccdis v cc value for stop of operation at v cc ramp-down ( 51 ) 6.8 v control voltages on hposf pin and v cc for soft start/stop operation ( 19 )( 52 ) v hon threshold for start/stop of h-drive sig- nal 1v v bon threshold for start/stop of b-drive sig- nal 1.7 v v hbnorm threshold for full operation duty cycle of h-drive and b-drive signals 2.4 v ccstop minimum supply voltage when voltage on hposf pin reaches v hon thresh- old ( 54 ) 4.8 v . bl an k h . l oc k no yes yes yes no no yes no t hh moire ? t h ---------------------------- -
STV6889 20/56 notes about miscellaneous section note 49: current sunk by the pin if the external voltage is higher than one the circuit tries to force. note 50: see v refo in section 6.2 . note 51: in the regions of v cc where the device's operation is disabled, the h-drive, v-drive and b+-drive signals on hout , vout and bout pins, resp., are inhibited, the i2c-bus does not accept any data and the xrayalarm flag is reset. also see figure 10 . note 52: see figure 10 . note 53: when v cc is below v ccxrayen xray detection and protection are disabled. note 54: minimum momentary supply voltage to ensure a correct performance of soft stop function at v cc fall down is defined at the moment when the voltage on hposf pin reaches v hon threshold.
STV6889 21/56 7 typical output waveforms table 7. typical output waveforms - note 55 function sad pin byte waveform effect on screen vertical size 07 vout (23) x0000000 x1111111 vertical size after gain 1d vout (23) x0000000 x1111111 vertical position 08 vout (23) x0000000 x1000000 x1111111 vertical position offset 1e vout (23) x0000000 x1000000 x1111111 s-correction 09 vout (23) x0000000: null x1111111: max. v mid(vout) v amp v mid(vout) v amp v mid(vout) v amp v mid(vout) v amp v mid(vout) v midref v mid(vout) v midre f v mid(vout) v midref v mid(vout) v midref v mid(vout) v midre f v mid(vout) v midref t vr 0 ? t vr t vr v amp t vr 0 ? t vr ? t vr t vr v amp v scor
STV6889 22/56 c-correction 0a vout (23) x0000000 x1000000 : null x1111111 vertical moir amplitude 0b vout (23) x0000000: null x1111111: max. horizontal size 10h ewout (24) 00000000 11111111 keystone correction 0d ewout (24) x0000000 x1111111 pin cushion correction 0c ewout (24) x0000000 x1111111 table 7. typical output waveforms - note 55 function sad pin byte waveform effect on screen t vr 0 ? t vr t vr v amp v ccor t vr 0 ? t vr t vr v amp t vr 0 ? t vr t vr v amp v ccor t nt v (n+1)t v (n-1)t v v amp t nt v (n+1)t v (n-1)t v v v-m oir v amp t vr 0 ? t vr t vr v ew-dc t vr 0 ? t vr t vr v ew-dc v ew-key t vr 0 ? t vr t vr v ew-dc v ew-key v ew-dc t vr 0 ? t vr t vr v ew-pcc t vr 0 ? t vr t vr v ew-pcc
STV6889 23/56 top corner correction 0e ewout (24) x1111111 x0000000 bottom corner correction 0f ewout (24) x1111111 x0000000 pin cushion s-correction 19 ewout (24) x1111111 x0000000 pin cushion w-correction 1a ewout (24) x1111111 x0000000 parallelogram correction 12h x0000000 x1111111 pin cushion asymmetry correction 11h x0000000 x1111111 table 7. typical output waveforms - note 55 function sad pin byte waveform effect on screen t vr 0 ? t vr t vr v ew-tcor t vr 0 ? t vr t vr v ew-tcor t vr 0 ? t vr t vr v ew-bcor t vr 0 ? t vr t vr v ew-bcor 0 ? t vr t vr t vr v ew-s 0 ? t vr t vr t vr v ew-s 0 ? t vr t vr t vr v ew-w 0 ? t vr t vr t vr v ew-w internal static h-phase t vr 0 ? t vr t vr t paralc static h-phase t vr 0 ? t vr t vr t paralc internal t vr 0 ? t vr t vr static h-phase t pcac t vr 0 ? t vr t vr static h-phase t pcac
STV6889 24/56 note 55: for any h and v correction component of the waveforms on ewout and vout pins and internal waveform for corrections of h asymmetry, displayed in the table, the weight of the other relevant components is nullified (minimum for parabola, s-correction, medium for keystone, all corner corrections, c-correction, s- and w-pin cushion corrections, parallelogram, pin cushion asymmetry correction, written in corresponding registers). top corner asymmetry correction 13h x0000000 x1111111 bottom corner asymmetry correction 14h x0000000 x1111111 vertical dynamic correction amplitude 15h vdycor (32) 01111111 application dependent x0000000 11111111 table 7. typical output waveforms - note 55 function sad pin byte waveform effect on screen internal t vr 0 ? t vr t vr static h-phase t tcac t vr 0 ? t vr t vr static h-phase t tcac internal t vr 0 ? t vr t vr static h-phase t bcac t vr 0 ? t vr t vr static h-phase t bcac t vr 0 ? t vr t vr vdycorpol=0 v vd-v v vd-dc t vr 0 ? t vr t vr v vd-d c v vd-v t vr 0 ? t vr t vr vdycorpol=1 v vd-d c v vd-v
STV6889 25/56 8 i2c-bus control register map the device slave address is 8c in write mode and 8d in read mode. the control register map is given in table . bold weight denotes default value at power-on-reset. i2c-bus data in the adjustment register is buffered and internally applied with discharge of the vertical os- cillator ( 56 ) . in order to ensure compatibility with future devices, all ?reserved? bits should be set to 0. table 8. i2c-bus control registers sadd7 d6d5d4d3d2d1d0 write mode (slave address = 8c) 00 hdutysyncv 1: synchro. 0 : asynchro. hduty horizontal duty cycle 0 0 0 0 0 0 0 01 hpos horizontal position 1 0000000 02 hmoirmode 1: separated 0 : combined hmoire horizontal moir amplitude 0000000 03 b+syncv 0 : asynchro. bref b+reference 1000000 04 reserved 05 reserved 06 boutpol 0 : type n reserved 07 boutph 0 : h-flyback 1: h-drive vsize ver tical size 1000000 08 ewtrhfr 0 : no tracking vpos vertical position 1000000 09 reserved scor s-correction 1000000 0a reserved ccor c-correction 1000000 0b reserved vmoire vertical moir amplitude 0000000 0c reserved pcc pin cushion correction 1000000 0d reserved keyst keystone correction 1000000 0e reserved tcc top corner correction 1000000 0f reserved bcc bottom corner correction 1000000 10 hsize horizontal size 1 0000000
STV6889 26/56 note 56: with exception of hduty and bref adjustments data that can take effect instantaneously if switches hdutysyncv and b+syncv are at 0, respectively. note 57: in read mode, the device always outputs data of the status register, regardless of sub address previously selected. note 58: the tv, th, tvm and thm bits are for testing purposes and must be kept at 0 by application. 11 reserved pcac pin cushion asymmetry correction 1000000 12 reserved pa r a l parallelogram correction 1000000 13 reserved tcac top corner asymmetry correction 1000000 14 reserved bcac bottom corner asymmetry correction 1000000 15 vdycorpol 0 : ? " vdc-amp vertical dynamic correction 1000000 16 xrayreset 0 : no effect 1: reset vsyncauto 1 : on vsyncsel 0:comp 1 :sep sdetreset 0 : no effect 1: reset pll1pump 1,1: fastest 0,0 : slowest pll1inhen 1 : on hlocken 1 : on 17 tv 0 : off ( 58 ) th 0 : off ( 58 ) tvm 0 : off ( 58 ) thm 0 : off ( 58 ) bohedge 0 : falling hbouten 0 : disable vouten 0 : disable blankmode 1 : perm. 18 reserved 19 reserved 0 : ewsc east-west s-correction 1000000 1a reserved 0 : ewwc east-west w-correction 1000000 1b reserved 0 : hehtg horizontal eht compensation gain 0000000 1c reserved 0 : vehtg vertical eht compensation gain 0000000 1d reserved 0 : vsag vertical size after-gain 1110000 1e reserved 0 : vpof vertical position offset 1000000 1f thrblsense 0: high bmute 0 : off bsafeen 0 : disable ewtrhsize 0 : tracking ident 0: no effect hlockspeed 0: slow reserved reserved read mode (slave address = 8d) xx ( 57 ) hlock 0: locked 1 : not locked vlock 0: locked 1 : not lock. xrayalarm 1: on 0 : off polarity detection sync detection hvpol 1 : negative vpol 1 : negative vextrdet 0 : not det. hvdet 0 : not det. vdet 0 : not det. table 8. i2c-bus control registers sadd7 d6d5d4d3d2d1d0
STV6889 27/56 description of i2c-bus switches and flags write-to bits sad00h/d7 - hdutysyncv sync hronization of internal application of h ori- zontal duty cycle data, buffered in i2c-bus latch, with internal discharge of v ertical oscillator. 0: asynchronous mode, new data applied with ack bit of i2c-bus transfer on this sub address 1: synchronous mode sad02h/d7 - hmoirmode h orizontal moir characteristics. 0: adapted to an architecture with eht gener- ated in deflection section 1: adapted to an architecture with separated deflection and eht sections sad03h/d7 - b+syncv same as hdutysyncv , applicable for b+ refer- ence data sad06h/d7 - boutpol pol arity of b+ drive signal on bout pin. 0: adapted to n type of power mos - high level to make it conductive 1: adapted to p type of power mos - low level to make it conductive sad07h/d7 - boutph ph ase of start of b+ drive signal on bout pin 0: end of horizontal flyback or horizontal fre- quency divided by 2, see bohedge bit. 1: with one of edges of line drive signal on hout pin, selected by bohedge bit sad08h/d7 - ewtrhfr tr acking of all corrections contained in wave- form on pin ewout with h orizontal fr equency 0: not active 1: active sad15h/d7 - vdycorpol pol arity of v ertical dy namic cor rection wave- form (parabola) 0: concave (minimum in the middle of the pa- rabola) 1: convex (maximum in the middle of the pa- rabola) sad16h/d0 - hlocken enable of output of h orizontal pll1 lock /unlock status signal on pin hlckvbk 0: disabled, vertical blanking only on the pin hlckvbk 1: enabled sad16h/d1 - pll1inhen en able of inh ibition of horizontal pll1 during extracted vertical synchronization pulse 0: disabled, pll1 is never inhibited 1: enabled sad16h/d2 and d3- pll1pump horizontal pll1 charge pump current sad16h/d4 - sdetreset reset to 0 of s ynchronization det ection flags vdet , hvdet and vextrdet of status register ef- fected with ack bit of i2c-bus data transfer into register containing the sdetreset bit. also see description of the flags. 0: no effect 1: reset with automatic return of the bit to 0 sad16h/d5 - vsyncsel v ertical sync hronization input sel ection be- tween the one extracted from composite hv sig- nal on pin h/hvsyn and the one on pin vsyn . no effect if vsyncauto bit is at 1. 0: v. sync extracted from composite signal on h/hvsyn pin selected 1: v. sync applied on vsyn pin selected sad16h/d6 - vsyncauto v ertical sync hronization input selection auto- matic mode. if enabled, the device automatically selects between the vertical sync extracted from composite hv signal on pin h/hvsyn and the one on pin vsyn , based on detection mechanism. if both are present, the one coming first is kept. 0: disabled, selection done according to bit vsyncsel 1: enabled, the bit vsyncsel has no effect d3 d2 time constant 0 0 slowest pll1, lowest current 1 0 moderate slow pll1, low current 0 1 moderate fast pll1, high current 1 1 fastest pll1, highest current
STV6889 28/56 sad16h/d7 - xrayreset reset to 0 of xray flag of status register effect- ed with ack bit of i2c-bus data transfer into reg- ister containing the xrayreset bit. also see de- scription of the flag. 0: no effect 1: reset with automatic return of the bit to 0 sad17h/d0 - blankmode blank ing operation mode . 0: blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge (start of vertical sawtooth ramp on the vout pin) 1: permanent blanking - high blanking level in composite signal on pin hlckvbk is perma- nent sad17h/d1 - vouten v ertical out put en able. 0: disabled, v offvout on vout pin (see section 6.5 vertical section ) 1: enabled, vertical ramp with vertical position offset on vout pin sad17h/d2 - hbouten h orizontal and b + out put en able. 0: disabled, levels corresponding to ?power transistor off? on hout and bout pins (high for hout , high or low for bout , depending on boutpol bit). 1: enabled, horizontal deflection drive signal on hout pin providing that it is not inhibited by another internal event (activated xray protection). b+ drive signal on bout pin if not inhibited by another internal event. programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and, if this is not inhibited by another inter- nal event, also the soft start of b+ dc/dc con- vertor controller. see also bits bmute and bsa- feen . sad17h/d3 - bohedge if the bit boutph is at 1, selection of edge of h or- izontal drive signal to phase b + drive o utput sig- nal on bout pin. 1: rising edge 0: falling edge if the bit boutph is at 0, selection of signal to phase b + drive output on bout pin: 1: horizontal frequency divided by 2 signal, top of horizontal vco 0: end of horizontal flyback sad17h/d4,d5,d6,d7 - thm , tvm , th , tv test bits. they must be kept at 0 level by appli- cation s/w. sad1fh/d2 - hlockspeed response speed of lock-to-unlock transition of h-lock component on hlock output and hlock i2c-bus flag at signal change. 0: low 1: high sad1fh/d3 - ident device ident ification bit. if hbouten is at 1, the bit has no effect. if hbouten is at 0, then 0: the value of hlock status bit is 1 1: the value of hlock status bit is 0 sad1fh/d4 - ewtrhsize tr acking of all corrections contained in wave- form on pin ew out with h orizontal size i2c-bus register hsize . 0: active 1: not active sad1fh/d5 - bsafeen b + output safe ty en able. 0: disabled 1: enabled, bout goes off as soon as hlock status of horizontal pll1 indicates ?unlock? state. retrieval of ?lock? state will initiate soft start mechanism of dc/dc controller on bout output. sad1fh/d6 - bmute b + output mute . 0: disabled 1: enabled, bout goes unconditionally off. programming this bit back to 0 will initiate soft start mechanism of dc/dc controller on bout output. sad1fh/d7 - thrblsense thr eshold on bisense input corresponding to current limitation. 0: high 1: low
STV6889 29/56 read-out flags sadxx/d0 - vdet ( 59 ) flag indicating det ection of v synchronization pulses on vsyn pin. 0: not detected 1: detected sadxx/d1 - hvdet ( 59 ) flag indicating det ection of h or h v synchroni- zation pulses applied on h/hvsyn pin. once the sync pulses are detected, the flag is set and latched. disappearance of the sync signal will not lead to reset of the flag. 0: not detected 1: detected. sadxx/d2 - vextrdet ( 59 ) flag indicating det ection of extr acted v ertical synchronization signal from composite h+v sig- nal applied on h/hvsyn pin. 0: not detected 1: detected sadxx/d3 - vpol flag indicating pol arity of v synchronization pulses applied on vsyn pin with respect to mean level of the sync signal. 0: positive 1: negative sadxx/d4 - hvpol flag indicating pol arity of h or h v synchroniza- tion pulses applied on h/hvsyn pin with respect to mean level of the sync signal. 0: positive 1: negative sadxx/d5 - xrayalarm alarm indicating that an event of excessive volt- age has passed on xray pin. can only be reset to 0 through i2c-bus bit xrayreset or by power- on reset. 0: no excess since last reset of the bit 1: at least one event of excess appeared since the last reset of the bit, hout inhibited sadxx/d6 - vlock status of ? lock ing? or stabilizing of v ertical oscil- lator amplitude to an internal reference by agc regulation loop. 0: locked (amplitude stabilized) 1: not locked (amplitude non-stabilized) sadxx/d7 - hlock loc k status of h orizontal pll1. 0: locked 1: not locked see also bit ident ( sad1fh/d3) note 59: this flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last reset (by means of the sdetreset i2c-bus bit). this is to be taken into account by application s/w in a way that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided between reset of the flag through sdetreset bit and validation of information provided in the flag after read-out of status register.
STV6889 30/56 9 operating description 9.1 supply and control 9.1.1 power supply and voltage references the device is designed for a typical value of power supply voltage of 12 v. in order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value of v cc is monitored. see figure 1 and electrical spec- ifications. at switch-on, the device enters a ?nor- mal operation? as the supply voltage exceeds v c- cen and stays there until it decreases bellow v c- cdis . the two thresholds provide, by their differ- ence, a hysteresis to bridge potential noise. out- side the ?normal operation?, the signals on hout , bout and vout outputs are inhibited and the i2c- bus interface is inactive (high impedance on sda , scl pins, no ack), all i2c-bus control registers be- ing reset to their default values (see chapter 8 - page 25 ). the stop of hout and bout drive signals when the v cc falls from normal operation below v ccdis is not instantaneous. it is only a trigger point of soft stop mechanism (see subsection 9.3.7- page 35 ). figure 1. supply voltage monitoring internal thresholds in all parts of the circuit are de- rived from a common internal reference supply v refo that is lead out to refout pin for external filter- ing against ground as well as for external use with load currents limited to i refo . the filtering is neces- sary to minimize interference in output signals, causing adverse effects like e.g. jitter. 9.1.2 i2c-bus control the i2c-bus is a 2 line bidirectional serial commu- nication bus introduced by philips. for its general description, refer to corresponding philips i2c-bus specification. this device is an i2c-bus slave, compatible with fast (400khz) i2c-bus protocol, with write mode slave address of 8ch (read mode slave address 8dh). integrators are employed at the scl (serial clock) input and at the input buffer of the sda (se- rial data) input/output to filter off the spikes up to 50ns. the device supports multiple data byte messages (with automatic incrementing of the i2c-bus subad- dress) as well as repeated start condition for i2c- bus subaddress change inside the i2c-bus mes- sages. all i2c-bus registers with specified i2c-bus subaddress are of write only type, whereas the status register providing a feedback informa- tion to the master i2c-bus device has no attributed i2c-bus subaddress and is of read only type. the master i2c-bus device reads this register sending directly, after the start condition, the read device i2c-bus slave address (8dh) fol- lowed by the register read-out, nak (no acknowl- edge) signal and the stop condition. for the i2c-bus control register map, refer to chap- ter 8 - page 25 . 9.2 synchronization processor 9.2.1 synchronization signals the device has two inputs for ttl-level synchroni- zation signals, both with hysteresis to avoid erratic detection and with a pull-down resistor. on h/ hvsyn input, pure horizontal or composite horizon- tal/vertical signal is accepted. on vsyn input, only pure vertical sync. signal is accepted. both posi- tive and negative polarities may be applied on ei- ther input, see figure 2 . polarity detector and pro- grammable inverter are provided on each of the two inputs. the signal applied on h/hvsyn pin, af- ter polarity treatment, is directly lead to horizontal part and to an extractor of vertical sync. pulses, working on principle of integration, see figure 3 . the vertical sync. signal applied to the vertical de- flection processor is selected between the signal extracted from the composite signal on h/hvsyn in- put and the one applied on vsyn input. the selec- tor is controlled by vsyncsel i2c-bus bit. besides polarity detection, the device is capable of detecting presence of sync. signals on each of the inputs and at the output of vertical sync. extractor. the information from all detectors is provided in the i2c-bus status register (5 flags: vdet , hvdet , normal operation hysteresis t disabled disabled v (vcc) v cc v ccen v ccdis
STV6889 31/56 vextrdet , vpol , hvpol ). the device is equipped with an automatic mode (switched on or off by vsyncauto i2c-bus bit) that also uses the detec- tion information. figure 2. horizontal sync signal 9.2.2 sync. presence detection flags the sync. signal presence detection flags in the status register ( vdet , hvdet , vextrdet ) do not show in real time the presence or absence of cor- responding sync. signal. they are latched to 1 as soon as a single sync. pulse is detected. in order to reset them to 0 (all at once), a 1 must be written into sdetreset i2c-bus bit, the reset action taking effect with ack bit of the i2c-bus transfer to the register containing sdetreset bit. the detection circuits are ready to capture another event (pulse). see note 59 . figure 3. extraction of v-sync signal from h/v-sync signal 9.2.3 mcu controlled sync. selection mode i2c-bus bit vsyncauto is set to 0. the mcu reads the polarity and signal presence detection flags, after setting the sdetreset bit to 1 and an appro- priate delay, to obtain a true information of the sig- nals applied, reads and evaluates this information and controls the vertical signal selector according- ly. the mcu has no access to polarity inverters, they are controlled automatically. see also chapter chapter 8 - page 25 . 9.2.4 automatic sync. selection mode i2c-bus bit vsyncauto is set to 1. in this mode, the device itself controls the i2c-bus bits switching the polarity inverters ( hvpol , vpol ) and the vertical sync. signal selector ( vsyncsel ), using the infor- mation provided by the detection circuitry. if both extracted and pure vertical sync. signals are present, the one already selected is maintained. no intervention of the mcu is necessary. positive negative t h t pulsehsyn h/v-sync integration extracted t h v-sync internal t pulsehsyn t extrv
STV6889 32/56 9.3 horizontal section 9.3.1 general the horizontal section consists of two plls with various adjustments and corrections, working on horizontal deflection frequency, then phase shift- ing and output driving circuitry providing h-drive signal on hout pin. input signal to the horizontal section is output of the polarity inverter on h/hvsyn input. the device ensures automatically that this polarity be always positive. 9.3.2 pll1 the pll1 block diagram is in figure 5 . it consists of a voltage-controlled oscillator (vco), a shaper with adjustable threshold, a charge pump with inhi- bition circuit, a frequency and phase comparator and timing circuitry. the goal of the pll1 is to make the vco ramp signal match in frequency the sync. signal and to lock this ramp in phase to the sync. signal. on the screen, this offset results in the change of horizontal position of the picture. the loop, by tuning the vco accordingly, gets and maintains in coincidence the rising edge of input sync. signal with signal ref1, deriving from the vco ramp by a comparator with threshold adjust- able through hpos i2c-bus control. the coinci- dence is identified and flagged by lock detection circuit on pin hlckvbk as well as by hlock i2c-bus flag. the charge pump provides positive and negative currents charging the external loop filter on hpll1f pin. the loop is independent of the trailing edge of sync. signal and only locks to its leading edge. by design, the pll1 does not suffer from any dead band even while locked. the speed of the pll1 depends on current value provided by the charge pump. while not locked, the current is very low, to slow down the changes of vco frequency and thus protect the external power components at sync. signal change. in locked state, the currents are much higher, four different values being se- lectable via pll1pump i2c-bus bits to provide a means to control the pll1 speed by s/w. lower value make the pll1 slower, but more stable. higher values make it faster and less stable. in general, the pll1 speed should be higher for high deflection frequencies. the response speed and stability (jitter level) depend on the choice of exter- nal components making up the loop filter. a ?crc? filter is generally used (see figure 4 ). figure 4. h-pll1 f ilter configuration the pll1 is internally inhibited during extracted vertical sync. pulse (if any) to avoid taking into ac- count missing or wrong pulses on the phase com- parator. inhibition is obtained by forcing the charge pump output to high impedance state. the inhibi- tion mechanism can be disabled through pll1inhen i2c-bus bit. the figure 7 , in its upper part, shows the position of the vco ramp signal in relation to input sync. pulse for three different positions of adjustment of horizontal position control hpos . r 2 c 1 c 2 hpll1f 9
STV6889 33/56 figure 5. horizontal pll1 block diagram figure 6. horizontal oscillat or (vco) schematic diagram 9.3.3 voltage controlled oscillator the vco makes part of both pll1 and pll2 loops, being an ?output? to pll1 and ?input? to pll2. it delivers a linear sawtooth. figure 6 ex- plains its principle of operation. the linears are ob- tained by charging and discharging an external ca- pacitor on pin co , with currents proportional to the current forced through an external resistor on pin ro , which itself depends on the input tuning volt- age v ho (filtered charge pump output). the rising and falling linears are limited by v hothrlo and v ho- thrhi thresholds filtered through hoscf pin. at no signal condition, the v ho tuning voltage is clamped to its minimum (see section 6.4 - page 10), which corresponds to the free-running vco frequency f ho(0) . refer to subsection 9.3.1 for formu- la to calculate this frequency using external com- ponents values. the ratio between the frequency corresponding to maximum v ho and the one corre- sponding to minimum v ho (free-running frequen- cy) is about 4.5. this range can easily be in- creased in the application. the pll1 can only lock to input frequencies falling inside these two limits. pll inhibition shaper low high lock comp charge pump vco hosc (i2c) input interface sync v-sync (extracted) (i2c) detector polarity v-sync extracted ref1 (i2c) (i2c) pll1 hpll1f ro co hoscf hpos hposf pll1pump h/hvsyn hlckvbk blank hlock pll1inhen 3 9 8 6 4 10 1 rs flip-flop 4 i 0 i 0 2 i 0 + - (pll1 filter) + - + - from charge pump vco discharge control hoscf hpll1f co ro v ho v hothrhi v hothrlo v hothrhi v hothrlo 4 6 8 9
STV6889 34/56 9.3.4 pll2 the goal of the pll2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a cer- tain threshold of the vco sawtooth. this internal threshold is affected by geometry phase correc- tions, like e.g., parallelogram. the pll2 is fast enough to be able to follow the dynamism of phase modulation, this speed is strongly related to the value of the capacitor on hpll2c . the pll2 con- trol current (see figure 7 ) is significantly increased during discharge of vertical oscillator (during verti- cal retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. the pll2 control current is integrated on the external filter on pin hpll2c to obtain smoothed voltage, used, in comparison with vco ramp, as a threshold for h-drive rising edge generation. as both leading and tra iling edges of the h-drive signal in the figure 7 must fall inside the rising part of the vco ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of h-drive signal with maximum duty cycle. yet, the constraints thereof must be taken into account while consider- ing the application frequency range and h-flyback duration. the figure 7 also shows regions for rising and falling edges of the h-drive signal on hout pin. as it is forced high during the h-flyback pulse and low during the vco discharge period, no edge during these two events takes effect. the flyback input configuration is in figure 8 . 9.3.5 dynamic pll2 phase control the dynamic phase control of pll2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. it is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchroniza- tion). inside the device, the threshold v s(0) is com- pared with the vco ramp, the pll2 locking the middle of h-flyback to the moment of their match. the dynamic phase is obtained by modulation of the threshold by correction waveforms. refer to figure 14 and chapter 7 - page 21 . the correction waveforms have no effect in vertical middle of the screen (for middle vertical position). as they are summed, their effect on the phase tends to reach maximum span at top and bottom of the picture. as all the components of the resulting correction waveform (linear for parallelogram correction, pa- rabola of 2nd order for pin cushion asymmetry cor- rection and half-parabolas of 4th order for corner corrections independently at the top and at the bottom) are generated from the output vertical de- flection drive waveform, they all track with real ver- tical amplitude and position, thus being fixed on the screen. refer to chapter 8 - page 25 for details on i2c-bus controls. figure 7. horizontal timing diagram figure 8. hfly input configuration h-fly-back pll2 h-drive current control + - (on hout) t s h-drive region h-drive region inhibited t s : hot storage time h-osc 7/8t h t h max. med. min. h-sync (polarized) ref1 min max (i2c) max. med. min. pll1 lock (internal) (vco) pll2 pll1 control on forced high forced low off on hpos v hothrhi v hothrlo v thrhfly v hposf v s(0) t ph (max) t hph t hoff ~ 20k ~ 500 int. ext. hfly gnd 12
STV6889 35/56 9.3.6 output section the h-drive signal is inhibited (high level) during flyback pulse, and also when v cc is too low, when x-ray protection is activated ( xrayalarm i2c-bus flag set to 1) and when i2c-bus bit hbouten is set to 0 (default position). the duty cycle of the h-drive signal is controlled via i2c-bus register hduty . this is overruled dur- ing soft-start and soft-stop procedures (see section 9.3.7 and figure 10 ). the pll2 is followed by a rapid phase shifting which accepts the signal from h-moir canceller (see section 9.3.8 ) the output stage consists of a npn bipolar tran- sistor, the collector of which is routed to hout pin (see figure 9 ). figure 9. hout configuration 9.3.7 soft-start and soft-stop on h-drive the soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the h-drive signal, either via hbouten i2c-bus bit or after re- set of xrayalarm i2c-bus flag, to protect external power components. by its second function, the ex- ternal capacitor on pin hposf is used to time out this procedure, during which the duty cycle of h- drive signal starts at its maximum ( t hoff for soft start/stop in electrical specifications) and slowly decreases to the value determined by the control i2c-bus register hduty (vice versa at soft-stop). this is controlled by voltage on pin hposf . in case of supply voltage switch off, the transients on hout and bout have different characteristics. see figure 10 , figure 11 and section 9.8.1 . 9.3.8 horizontal moir cancellation the horizontal moir canceller is intended to blur a potential beat between the horizontal video pixel period and the crt pixel width, which causes vis- ible moir patterns in the picture. it introduces a microscopic indent on horizontal scan lines by injecting little controlled phase shifts to output circuitry of the horizontal section. their amplitude is adjustable through hmoire i2c-bus control. the behaviour of horizontal moir is to be opti- mized for different deflection design configurations using hmoirmode i2c-bus bit. this bit is to be kept at 0 for common architecture (b+ and eht common regulation) and at 1 for separated archi- tecture (b+ and eht each regulated separately). the maximum amplitude adjustable though hmoi- re i2c-bus control is optimized according to selec- tion by hmoirmode i2c-bus bit: larger when b+ and eht are each regulated separately, smaller when b+ and eht are common regulation. int. ext. hout 26
STV6889 36/56 figure 10. control of hout and bout at start/stop at nominal v cc figure 11. events triggering soft start and soft stop t soft start soft stop normal operation start h-drv start b-drv stop h-drv stop b-drv h-duty cycle b-duty cycle 100% 0% (i2c) minimum value maximum value hpos range v (hposf) hout bout (positive) v hposf v hon v bon v hbnorm t 100% 0% v (hposf) hout duty cycle bout duty cycle v hbnorm v bon v hon nominal v cc soft start event t 100% 0% v (hposf) hout duty cycle bout duty cycle falling v cc xrayalarm =0 v cc v ccdis v hbnorm v bon v hon v ccstop v hposf v hposf maximum v cc fall down speed for correct operation v hbnorm ? v bon ? v hon ? hbouten =1 v[ hposf ] v[ hposf ] soft stop event
STV6889 37/56 9.4 vertical section 9.4.1 general the goal of the vertical section is to drive vertical deflection output stage. it delivers a sawtooth waveform with an amplitude independent of de- flection frequency, on which vertical linearity cor- rections of c- and s-type are superimposed (see chapter 7 - page 21 ). block diagram is in figure 12 . the sawtooth is ob- tained by charging an external capacitor on pin vcap with controlled current and by discharging it via transistor q1. this is controlled by the con- troller. the charging starts when the voltage across the capacitor drops below v vob threshold. the discharging starts either when it exceeds v vot threshold (free run mode) or a short time after ar- rival of synchronization pulse. this time is neces- sary for the agc loop to sample the voltage at the top of the sawtooth. the v vob reference is routed out onto voscf pin in order to allow for further filtra- tion. the charging current influences amplitude of the sawtooth. just before the discharge, the voltage across the capacitor on pin vcap is sampled and compared to v votref . the comparison error voltage is stored on a storage capacitor connected on pin vagccap . this voltage tunes gain of the transcon- ductance amplifier providing the charging current in the next vertical period. speed of this agc loop depends on the storage capacitance on pin vagccap . the vlock i2c-bus flag is set to 1 when the loop is stabilized, i.e. when the tops of saw tooth on pin vcap match v vot value. on the screen, this corresponds to stabilized vertical size of picture. after a change of frequency on the sync. input, the stabilization time depends on the frequency difference and on the capacitor value. the lower its value, the shorter the stabilization time, but on the other hand, the lower the loop sta- bility. a practical compromise is a capacitance of 470nf. the leakage current of this capacitor re- sults in difference in amplitude between low and high frequencies. the higher its parallel resistance r l(vagccap) , the lower this difference. when the synchronization pulse is not present, the charging current is fixed. as a consequence, the free-running frequency f vo(0) only depends on the value of the capacitor on pin vcap . it can be rough- ly calculated using the following formula f vo(0) = the frequency range in which the agc loop can regulate the amplitude also depends on this ca- pacitor. the vertical sawtooth with regulated amplitude is lead to amplitude control stage. the discharge ex- ponential is replaced by v vob level, which, under control of the controller, creates a rapid fall- ing edge and a flat part before beginning of new ramp. the agc output signal passes through gain and position adjustment stages controlled through vsize and vpos i2c-bus registers. the resulting signal serves as input to all geometry correction circuitry including ew-drive signal, horizontal phase modulation and dynamic correction outputs. 9.4.2 s and c corrections for the sake of vertical picture linearity, the s- and c-corrections are now superimposed on the linear ramp signal. they both track with vsize and vpos adjustments to ensure unchanged linearity on the screen at changes of vertical size or vertical position. as these corrections are not included in the agc loop, their adjustment via ccor and scor i2c-bus registers, controlling shape of verti- cal output sawtooth affects by principle its peak-to- peak amplitude. however, this stage is conceived in a way that the amplitude be independent of these adjustments if vsize and vpos registers are set to their medium values. 9.4.3 vertical breathing compensation the signal provided with the linearity corrections is amplitude affected in a gain control stage, ruled by the voltage on vehtin input and its i2c-bus control vehtg . 9.4.4 vertical after-ga in and offset control another gain control is applied via vsag i2c-bus register. then an offset is added, its amount corre- sponding to vpof i2c-bus register value. these two controls result in size and position changes with no effect on shape of output vertical sawtooth or any geometry correction signal. c (vcap) . 100hz 150nf
STV6889 38/56 9.4.5 vertical moir to blur potential moir patterns due to interaction of deflection lines with crt mask grid, the picture position is to be slightly alternated at frame fre- quency. for this purpose, a square waveform at half-frame frequency is superimposed on the out- put waveform. its amplitude is adjustable through vmoire i2c-bus control. 9.4.6 biasing of vertical booster the biasing voltage for external dc-coupled verti- cal power amplifier is to be derived from v refo volt- age provided on pin refout , using a resistor divid- er, this to ensure the same temperature drift of mean (dc) levels on both differential inputs and to compensate for spread of v refo value (and so mean output value) between particular devices. figure 12. vertical section block diagram synchro polarity controller discharge sampling sampling capacitance c-correction charge current trans-conductance amplifier voscf vout vcap vsyn osc cap. q1 vehtin vagccap vsize (i2c) scor ( i2c ) ccor ( i2c ) vmoire (i2c) vpof (i2c) vsag (i2c) s-correction v vob internal v-ramp 22 20 18 23 19 2 vpos (i2c) sawtooth discharge v votref v midref to geometry processing vehtg (i2c) v vehtnull r r vpos (i2c) v midref v midref
STV6889 39/56 9.5 ew drive section the goal of the ew drive section is to provide, on pin ewout , a waveform which, used by an external dc-coupled power stage, serves to compensate for those geometry errors of the picture that are symmetric versus vertical axis across the middle of the screen. the waveform consists of an adjustable dc value, corresponding to horizontal size, a parabola of 2nd order for ?pin cushion? correction, a linear for ?key- stone? correction, independent half-parabolas of 4th order for top and bottom corner corrections, s- shape for ?s? correction and w shape for ?w? cor- rection. all of them are adjustable via i2c-bus, see chapter 8 - page 25 . refer to figure 14 , figure 15 and chapter chapter 7 - page 21 . the adjustments of these correction waveforms have no effect in the middle of the ver- tical scan period (if the vpos control is adjusted to its medium value). as they are summed, the re- sulting waveform tends to reach its maximum span at top and bottom of the picture. the voltage at the ewout is top and bottom limited (see parameter v ew ). according to figure 15 , especially the bottom limitation seems to be critical for maximum hori- zontal size (minimum dc). actually it is not critical since the parabola component must always be ap- plied to obtain a picture without pin cushion distor- tion. as all the components of the resulting correc- tion waveform are generated from an internal line- ar vertical sawtooth waveform bearing vsize and vpos adjustments, they all track with vertical am- plitude and position, thus being fixed vertically on the screen. they are not affected by c- and s-cor- rections, by prescale adjustments ( vsag and vpof ), by vertical breathing compensation and by vertical moire cancellation. the sum of compo- nents other than dc is conditionally affected by value in hsize i2c-bus control in reversed sense. refer to electrical specifications for value. this tracking with hsize can be switched off by ewtrhsize i2c-bus bit. the dc value, adjusted via hsize control, is also affected by voltage on hehtin input, thus providing a horizontal breathing compensation. the effect of this compensation is controlled by hehtg . the resulting waveform is conditionally multiplied with voltage on hpll1f , which depends on frequency. refer to electrical specifications for values. this tracking with fre- quency provides a rough compensation of varia- tion of picture geometry with frequency and allows to fix the adjustment ranges of i2c-bus controls throughout the operating range of horizontal fre- quencies. it can be switched off by ewtrhfr i2c- bus bit (off by default). the functionality is ex- plained in figure 13 . the upper part gives the influ- ence on dc component, the lower part on ac component, showing also the tracking with hsize . grey zones give the total span of breathing correc- tion using the whole range of input operating volt- age on hehtin input and whole range of adjust- ment of hehtg register. the ew waveform signal is buffered by an npn emitter follower, the emitter of which is directly routed to ewout output. it is internally biased (see electrical specifications for current value).
STV6889 40/56 figure 13. tracking of ewout signal with frequency min v ew-base v hothrfr v ew-dc min max v ho breathing hsize =max hsize =min min v ew-base v hothrfr v ew-dc min max v ho breathing h s i z e = m a x hsize =min ewtrhfr =1 ewtrhfr =0 v hothrfr v ew-ac min max v ho breathing h s i z e = m i n h s i z e = m a x ewtrhfr =1 v hothrfr v ew-ac min max v ho breathing hsize =min hsize =max ewtrhfr =0 0 breathing ewtrhsize =1 0 breathing ewtrhsize =1 breathing breathing
STV6889 41/56 figure 14. geometric correct ions? schematic diagram int. v-ramp to hpll2 tracking with hor. frequency controls: 1-quadrant 2-quadrant (linear, before corrections) vdycor ewout 24 hehtin x 2 x 4 x 3 32 17 internal dynamic phase waveform 9 hpll1f hehtg hsize ewtrhfr 1 0 v hothrfr 0v keyst pcc tcc bcc ewwc ewsc paral pcac tcac bcac keystone pin cushion top corner bot. corner ?w? ?s? parallelogram pin cushion asymmetry top corner asymmetry bottom corner asymmetry breathing v midref vdc-amp vdycorpol h-size control v vd-dc v hehtnull v ew-base 0v v ew (min) v ew (max) 0v ewtrhsize dc 0...2.5v tracking -1
STV6889 42/56 figure 15. ewout output waveforms keystone pcc top bottom corners ver tical sawtooth alone alone t vr 0t vr t vr t vr 00 alone salone walone non-linear region t vr 0 t vr 0 v heht (min) v ew-dc v heht v refo v hehtnull v heht (max) hsize (i2c) min. mid. max. v ew max min 0 hehtg (i2c) 00h 7fh 00h 7fh 00h 7fh v (vcap) v ew-key v ew-pcc v ew-tcor v ew-bcor v ew-s v ew-w tracking with frequency off. ( ewtrhfr = 0) non-linear region breathing compensation on dc
STV6889 43/56 9.6 dynamic correction outputs section 9.6.1 vertical dynamic correction output vdycor a parabola at vertical deflection frequency is avail- able on pin vdycor . its amplitude is adjustable via vdc-amp i2c-bus control and polarity controlled via vdycorpol i2c-bus bit. it tracks with real verti- cal amplitude and position. it is not affected by c- and s-corrections or breathing compensation. it does not track with vertical size after-gain (sad1dh) nor with vertical position offset (sad1eh) adjustments. the use of both correction waveforms is up to the application (e.g. dynamic focus, dynamic bright- ness control). 9.7 dc/dc controller section the section is designed to control a switch-mode dc/dc converter. a switch-mode dc/dc conver- tor generates a dc voltage from a dc voltage of different value (higher or lower) with little power losses. the dc/dc controller is synchronized to horizontal deflection frequency to minimize poten- tial interference into the picture. its operation is similar to that of standard uc3842. the schematic diagram of the dc/dc controller is in figure 16 . the bout output controls an external switching circuit (a mos transistor) delivering pulses synchronized on horizontal deflection fre- quency, the phase of which depends on h/w and i2c-bus configuration. see the table at the end of this chapter. their duration depends on the feed- back provided to the circuit, generally a copy of dc/dc converter output voltage and a copy of cur- rent passing through the dc/dc converter circuitry (e.g. current through external power component). the polarity of the output can be controlled by boutpol i2c-bus bit. a npn transistor open-collec- tor is routed out to the bout pin. during the operation, a sawtooth is to be found on pin bisense , generated externally by the applica- tion. according to boutph i2c-bus bit, the r-s flip- flop is set either at h-drive signal edge (rising or falling, depending on bohedge i2c-bus bit), or a certain delay ( t btrigdel ) after middle of h-flyback, or at horizontal frequency divided by two (phase cor- responding to v hothrhi on the vco ramp). the out- put is set on at the end of the short pulse generat- ed by the monostable trigger. timing of reset of the r-s flip-flop affects duty cy- cle of the output square signal and so the energy transferred from dc/dc converter input to its out- put. a reset edge is provided by comparator c2 if the voltage on pin bisense exceeds the internal threshold v thrbiscurr . this represents current limita- tion if a voltage proportional to the current through the power component or deflection stage is availa- ble on pin bisense . this threshold is affected by voltage on pin hposf , which rises at soft start and descends at soft stop. this ensures self-contained soft control of duty cycle of the output signal on pin bout . refer to figure 10 . another condition for reset of the r-s flip-flop, or-ed with the one described before, is that the voltage on pin bisense exceeds the voltage v c2 , which depends on the voltage ap- plied on input bregin of the error amplifier o1. the two voltages are compared, and the reset signal generated by the comparator c1. the error ampli- fier amplifies (with a factor defined by external components) the difference between the input voltage proportional to dc/dc convertor output voltage and internal reference v breg . the internal reference and so the output voltage is i2c-bus ad- justable by means of bref i2c-bus control. both step-up (dc/dc converter output voltage higher than its input voltage) and step-down (out- put voltage lower than input) can be built. 9.7.1 synchronization of dc/dc controller for sake of application flexibility, the output drive signal on bout pin can be synchronized with one of four events in table 9. for the first line case, the synchronization instant is every second top of hor- izontal vco saw tooth. see figure 7 . 9.7.2 soft-start and soft-stop on b-drive the soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the b-drive signal, either via hbouten i2c-bus bit or after re- set of xrayalarm i2c-bus flag, to protect external power component. see figure 10 and sub chapter safety functions on page 45 . the drive signal on bout pin can be switched off alone by means of bmute i2c-bus bit, without switching off the drive signal on pin hout . the switch-off is quasi-immediate, without the soft-stop procedure. at switching back on, the soft-start of the dc/dc controller is performed, timed by an in- ternal timing circuit, see figure 16 . when bsafeen i2c-bus bit is enabled, the drive signal on bout pin will go off as soon as the hori- zontal pll1 indicates unlocked state, without the soft-stop. resuming of locked state will initiate the soft-start mechanism of the dc/dc controller, timed by an internal timing circuit.
STV6889 44/56 table 9. idc/dc controlle r off-to-on edge timing figure 16. dc/dc converter controller block diagram boutph (sad07h/d7) bohedge (sad17h/d3) timing of off-to-on transition on bout output 0 1 vco ramp top at horizontal frequency divided by two 0 0 middle of h-flyback plus t btrigdel 1 0 falling edge of h-drive signal 1 1 rising edge of h-drive signal n type soft start h-drive edge h-fly-back + - + - + - ~500ns monostable p type feedback c2 (i2c) b-drive inhibition (i2c) (+delay) (i2c) 2r r v breg i1 i2 i3 v c2 o1 2 28 bout 16 bisense 10 hposf 14 bcomp 15 bregin boutpol boutph bohedge v thrbiscurr vco 1 0 1 0 1 0 v cc c1 s q r (safety functions) timing + - b-drive protection at h-unlock (safety functions) c3 safety block
STV6889 45/56 9.8 miscellaneous 9.8.1 safety functions the safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on h-drive and b-drive signals on hout and bout outputs, b-drive cut-off at unlock condition and x-ray protection. for supply voltage supervision, refer to subsection 9.1.1 and figure 1 . a schematic diagram putting to- gether all safety functions and composite pll1 lock and v-blanking indication is in figure 17 . 9.8.1.1 soft start and soft stop function for soft start and soft stop features for h-drive and b-drive signal, refer to subsection 9.3.7 and subsec- tion 9.7 , respectively. see also the figure 10 and figure 11 . regardless why the h-drive or b-drive signal are switched on or off (i2c-bus command, power up or down, x-ray protection), the signals always phase-in and phase-out in the way drawn in the figures, the first to phase-in and last to phase-out being the h-drive signal, which is to bet- ter protect the power stages at abrupt changes like switch-on and off. the timing of phase-in and phase-out depends on the capacitance connected to hposf pin which is virtually unlimited for this function. however, as it has a dual function (see subsection 9.3.2 ), a compromise thereof is to be found. the soft stop at power down condition can be con- sidered as a special case. as at this condition the thresholds v hon , v bon and v hbnorm depend on the momentary level of supply voltage (marked v hon ?, v bon ?, v hbnorm ? in figure 11 ), the timing of soft stop mechanism depends, apart from the capacitance on hposf , also on the falling speed of supply volt- age. the device is capable of performing a correct soft stop sequence providing that, at the moment the supply voltage reaches v ccstop , the voltage on hposf has already fallen below v hon ( section 9.8 ). 9.8.1.2 b-drive cut-off at unlock condition this function is described in subsection 9.7.2 . 9.8.1.3 x-ray protection the x-ray protection is activated if the voltage lev- el on xray input exceeds v thrxray threshold and if the v cc is higher than the voltage level v ccxrayen . as a consequence, the h-drive and b-drive signals on hout and bout outputs are inhibited (switched off) after a 2-horizontal deflection line delay provid- ed to avoid erratic excessive x-ray condition de- tection at short parasitic spikes. the xrayalarm i2c-bus flag is set to 1 to inform the mcu. this protection is latched; it may be reset either by v cc drop or by i2c-bus bit xrayreset (see chapter 8 - page 25 ).
STV6889 46/56 figure 17. safety functions - block diagram v cc supervision h-drive inhibition v-drive inhibition b-drive inhibition soft h-drive inhibit r s h-lock detector v-sync r s q + _ + _ v-sawtooth discharge i2c i2c i2c i2c i2c (timing) i2c i2c i2c i2c bit/flag pin int. signal v ccen v ccdis v thrhfly + _ v thrxray h-vco l2=h-lock/unlock level l1=no blank/blank level l3=l1+l2 in out q (overrule) b-drive inhibit discharge control i2c h-lock detector i2c pll1 pll2 dc/dc bmute bsafeen start & stop inhibition control hbouten xrayreset xrayalarm vouten blankmode hlocken hlock 10 hposf v ccxrayen v cc v cc + _ :2 enable 25 xray 12 hfly 3 hlckvbk x b-drive protection at h-unlock = start = stop 0=off 1=on
STV6889 47/56 9.8.2 composite output hlckvbk the composite output hlckvbk provides, at the same time, information about lock state of pll1 and early vertical blanking pulse. as both signals have two logical levels, a four level signal is used to define the combination of the two. schematic di- agram putting together all safety functions and composite pll1 lock and v-blanking indication is in figure 17 , the combinations, their respective lev- els and the hlckvbk configuration in figure 18 . the early vertical blanking pulse is obtained by a logic combination of vertical synchronization pulse and pulse corresponding to vertical oscillator dis- charge. the combination corresponds to the draw- ing in figure 18 . the blanking pulse is started with the leading edge of any of the two signals, which- ever comes first. the blanking pulse is ended with the trailing edge of vertical oscillator discharge pulse. the device has no information about the vertical retrace time. therefore, it does not cover, by the blanking pulse, the whole vertical retrace period. by means of blankmode i2c-bus bit, when at 1 (default), the blanking level (one of two ac- cording to pll1 status) is made available on the hlckvbk permanently. the permanent blanking, ir- respective of the blankmode i2c-bus bit, is also provided if the supply voltage is low (under v ccen or v ccdis thresholds), if the x-ray protection is ac- tive or if the v-drive signal is disabled by vouten i2c-bus bit. figure 18. levels on hlckvbk composite output hpll1 locked v-early blanking yes yes no yes no no yes no l1 (h) +l2 (l) l1 (l) +l2 (h) l1 (h) +l2 (h) l1 (l) +l2 (l) l1 - no blank/blank level l2 - h-lock/unlock level 3 hlckvbk v cc v olckbk i sinklckbk
STV6889 48/56 figure 19. ground layout recommendations general ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 STV6889
STV6889 49/56
STV6889 50/56 10 internal schematics figure 20. figure 21. figure 22. figure 23. figure 24. figure 25. 5v 200 1 h/hvsyn applies also for pin 2 ( vsyn ) 3 hlckvbk v refo v cc 12v 4 hoscf v refo 5 hpll2c v refo v cc 6 co v refo v cc 8 ro v refo v cc 3
STV6889 51/56 figure 26. figure 27. figure 28. figure 29. figure 30. figure 31. 9 hpll1f 12v 10 hposf v refo 12 hfly v cc 14 bcomp v cc 15 bregin v cc 16 bisense v cc 3
STV6889 52/56 figure 32. figure 33. figure 34. figure 35. figure 36. figure 37. 17 hehtin applies also for pin 18 ( vehtin ) v cc 19 voscf v refo v cc 20 vagccap v cc 22 vcap v cc 23 vout v cc 24 ewout applies also for pin 32 ( vdycor ) v cc 3
STV6889 53/56 figure 38. figure 39. figure 40. 25 xray v cc 26 hout applies also for pin 28 ( bout ) v cc 30 scl applies also for pin 31 ( sda ) v cc 3
STV6889 54/56 11 package mechanical data 32 pins - plastic shrink dimensions millimeters inches min. typ. max. min. typ. max. a 3.556 3.759 5.080 0.140 0.148 0.200 a1 0.508 0.020 a2 3.048 3.556 4.572 0.120 0.140 0.180 b 0.356 0.457 0.584 0.014 0.018 0.023 b1 0.762 1.016 1.397 0.030 0.040 0.055 c .203 0.254 0.356 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.906 10.41 11.05 0.390 0.410 0.435 e1 7.620 8.890 9.398 0.300 0.350 0.370 e 1.778 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.540 3.048 3.810 0.100 0.120 0.150 ea eb e1 e d 32 17 16 1 stand-off e b1 b a2 a1 a l c 4
STV6889 55/56 12 glossary ac a lternate c urrent ack ack nowledge bit of i2c-bus transfer agc a utomatic g ain c ontrol comp comp arator crt c athode r ay t ube dc d irect c urrent eht e xtra h igh v oltage ew e ast- w est h/w h ard w are hot h orizontal o utput t ransistor i 2 c i nter- i ntegrated c ircuit iic i nter- i ntegrated c ircuit mcu m icro- c ontroller u nit nand n egated and (logic operation) npn n egative- p ositive- n egative osc osc illator pll p hase- l ocked l oop pnp p ositive- n egative- p ositive ref ref erence rs, r-s r eset- s et s/w s oft w are ttl t ransistor t ransistor l ogic vco v oltage- c ontrolled o scillator 5
STV6889 56/56 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 6

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